Field of the Invention
The present invention relates to timing controllers and display devices. In particular, the present invention relates to a timing controller and a display device, which can inhibit an influence by applied exogenous noise from appearing on a liquid crystal display when the exogenous noise such as exogenous noise synchronizing with a synchronizing signal (such as HSYNC, VSYNC, or DE) or a transmission clock period is applied, and can be achieved without enlarging the size of a circuit.
Description of the Related Art
A timing controller for a liquid-crystal display device generates a control signal for a liquid crystal driving sorting driver and a liquid crystal driving gate driver based on a reference signal, such as HSYNC (horizontal synchronizing signal), VSYNC (vertical synchronizing signal), or DE (composite synchronizing signal), input into a liquid-crystal display device. Therefore, an incorrect control signal may be outputted, and a malfunction in which noise is generated or a screen is changed on a liquid crystal display may be caused when exogenous noise such as static electricity is mixed into a reference signal during display action.
Conventional timing controllers have had many configurations in which superimposition of noise synchronizing with each synchronizing signal and transmission clock period on synchronizing signals and image data fed from the outside has such an influence on the display of liquid-crystal display devices that the noise is recognized as a normal signal or a black screen is outputted depending on the size of the noise. In recent years, the number of users performing evaluation in which noise is intentionally introduced from the outside has been increased, so that immunity to synchronizing noise and the like has been needed.
FIG. 4 illustrates the configuration of a timing controller 12 in a conventional liquid-crystal display device, and FIG. 5 illustrates a conventional liquid-crystal display device 1.
In FIG. 5, the conventional liquid-crystal display device 1 includes: a liquid crystal display 2 including a plurality of scanning line electrodes 18 disposed at predetermined spacings in an X-direction, a plurality of signal line electrodes 17 disposed at predetermined spacings in a Y-direction, liquid crystal cells 51 that are sandwiched between the electrodes so that the electrodes intersect each other and that have equivalently formed capacitive loads, common electrodes (not illustrated), thin film transistors (TFTs) 50 for driving the corresponding liquid crystal cells 51, and capacitors 52 that accumulates data charge during one vertical synchronization period; a signal line electrode driving circuit 6 including one or more signal line driving source drivers IC8; a scanning line electrode driving circuit 3 including one or more scanning line driving gate drivers IC9; and a timing controller 12.
In FIG. 4, the timing controller 12 for a conventional display device includes: a receiver circuit unit 14 for synchronizing each synchronizing signal of HSYNC, VSYNC, and DE fed from the outside and an image data signal fed from the outside with a CLK signal fed from the outside; a timing generation unit 13 that generates a control signal VSP for driving a scanning line driving gate driver IC9 and a signal line driving source driver IC8 (start pulse signal for scanning line driving gate driver IC), VCK (clock signal for scanning line driving gate driver IC), a signal VOE for output control of a scanning line driving gate driver IC9 (output enable signal for scanning line driving gate driver IC), HSP (start pulse signal for signal line driving source driver IC), DLP (data latch pulse signal for signal line driving source driver IC), and POL (alternate-current driving polarity reversion signal); and an image data processing unit 15 that processes image data fed from the outside. Each synchronizing signal and image data outputted from the receiver circuit unit 14 are signals synchronized with CLK (clock signal) fed from the outside.
The timing controller 12 outputs the image data for each driver and the control signal VOE described above from timing information for display, based on a synchronizing signal, such as a clock (hereinafter “CLK”) or horizontal synchronizing signal (hereinafter “HSYNC”), a vertical synchronizing signal (hereinafter “VSYNC”), or a composite synchronizing signal (hereinafter “DE”), and image data, fed from the outside.
In the signal line electrode driving circuit 6, each signal line driving source driver IC8 takes image data at the timing of HSP (start pulse signal for signal line driving source driver IC), DLP (data latch pulse signal for signal line driving source driver IC), POL (alternate-current driving polarity reversion signal), and CLK outputted from the timing controller 12, and each item of image data in each pixel corresponding to one line is converted into a voltage value, which is fed to a pixel electrode in a panel for liquid crystals, corresponding to one line through a drain electrode in TFT.
The scanning line driving gate driver IC9 of the scanning line electrode driving circuit 3 controls all scanning line electrodes of each TFT as described above on a one-line basis in synchronism with a VCK signal based on VSP (start pulse signal for scanning line driving gate driver IC), VCK (clock signal for scanning line driving gate driver IC), and VOE (output enable signal for scanning line driving gate driver IC) outputted from the timing controller 12 and applies a gradation voltage, fed from the signal line driving source driver 8 at the time of conduction, to a pixel electrode by starting the sequential conduction of each TFT corresponding to one line in an upper or lower portion in the Y-direction.
In order to drive the liquid-crystal display device 1 as described above, synchronizing signals such as HSYNC, VSYNC, and DE are required for the timing controller 12, and a control signal for the scanning line driving gate driver IC9 and a control signal for a signal line driving source driver IC8 are generated from the synchronizing signals. Therefore, when external noise is superposed on synchronizing signals such as HSYNC, VSYNC, DE, and CLK, the control signals for the scanning line driving gate driver IC9 and the signal line driving source driver IC8 are synchronized with the incorrect synchronizing signals, on which the noise is superimposed, and therefore differ from normal control signals. When the control signals differ from a normal state, a phenomenon such as a display moved upward and downward with respect to a liquid crystal display (hereinafter “V synchronization displacement”), a display in which lines are horizontally formed (hereinafter “line noise”), the flicker of a screen (hereinafter “screen flash”), or stopping of a screen with a certain fixed color (hereinafter “fixed-colored screen display) is caused (hereinafter “malfunction state”).